Alif Semiconductor /AE512F80F5582LS_CM55_HE_View /SDMMC /SDMMC_SW_RST_R

Software Reset for All. This reset affects the entire Host Controller except for the card detection circuit. During its initialization, the Host Driver sets this bit to 0x1 to reset the Host Controller. All registers are reset except the capabilities register (SDMMC_CAPABILITIES1_R and SDMMC_CAPABILITIES2_R). If this bit is set to 0x1, the Host Driver must issue reset command and reinitialize the card.

0 (Val_0x0): Work

1 (Val_0x1): Reset

Software Reset for CMD line. This bit resets only a part of the command circuit to be able to issue a command. This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit for CMD line control) and does not affect the data transfer circuit. Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. The following registers and bits are cleared by this bit:

• SDMMC_PSTATE_REG register: CMD_INHIBIT bit
• SDMMC_NORMAL_INT_STAT_EN_R register: Command Complete bit
• SDMMC_ERROR_INT_STAT_EN_R register: Response error statuses related to CMD_INHIBIT bit

0 (Val_0x0): Work

1 (Val_0x1): Reset

Software Reset for DAT line. This bit is used in SD or eMMC modes and it resets only a part of the data circuit and the DMA circuit is also reset. The following registers and bits are cleared by this bit: SDMMC_BUF_DATA_R register:

• Buffer is cleared and initialized. SDMMC_PSTATE_REG register:
• Buffer Read Enable
• Buffer Write Enable
• Read Transfer Active
• Write Transfer Active
• DAT Line Active
• Command Inhibit (DAT) SDMMC_BGAP_CTRL_R register:
• Continue Request
• Stop at Block Gap Request SDMMC_NORMAL_INT_STAT_EN_R register:
• Buffer Read Ready
• Buffer Write Ready
• DMA Interrupt
• Block Gap Event
• Transfer Complete

0 (Val_0x0): Work

1 (Val_0x1): Reset